Memory-processor co-scheduling for real-time tasks on network-on-chip manycore architectures

The network-on-chip (NoC) provides a viable solution to bus-contention problems, that occur in classical manycore architectures. However, NoC complex design requires particular attention support the execution of real-time workloads. In this paper, we consider task-to-core allocation and inter-task communications, guarantee respect timing constraints. addition, address task-to-main-memory as it generates additional traffic. Rather than separating problems allocation, memory-to-task data transfers separately, tackle these at same time for set tasks modeled using directed acyclic graphs (DAGs). We propose an algorithm sequence transformations simplify problem resolving handle its combinatorial explosion. evalaute effectiveness proposed approaches large synthetic experiments.